Asian Journal of Information Technology
ISSN: Online 1993-5994ISSN: Print 1682-3915
Abstract
Outstanding bit error rate LDPC design in waterfall region and error floor region is one of the challenging tasks for the past decade. In this study, we focus the design of LDPC encoder with low the error floor and waterfall region of BER with minimum trapping set Scheduled Progressive Edge Growth (SPEG) LDPC encoder innovatively, the simulation result of density evolution and exit chart give the better convergence of LDPC encoder, BER performance in error floor can controlled by minimum trapping set and waterfall region controlled by scheduled PEG LDPC encoder with (1000, 500) with code length (n) is <600. The girth of the SPEG encoder is 8. SPEG with minimum trapping set will perform well for short length code also and it converges faster than the other PEG encoder.
How to cite this article:
A. Anand and P. Senthilkumar. Scheduled Progressive Edge Growth LDPC Encoder with Minimum Trapping Set.
DOI: https://doi.org/10.36478/ajit.2016.2162.2166
URL: https://www.makhillpublications.co/view-article/1682-3915/ajit.2016.2162.2166