Research Journal of Applied Sciences
ISSN: Online 1993-6079ISSN: Print 1815-932x
Abstract
In this research, researchers propose a memory-efficient on-chip network architecture based router design. In addition to the resource utilization of router design, the high requirements of memories in router architecture design increases the network latency. To overcome such drawback, researchers have developed an optimized weighted scheduling methodology for router architecture and integrated it in the NI such that the network and memory latencies are significantly reduced. This proposed reliable network-on-chip router can reduce faults in both the router components and the reliability components in real time environment. The area overhead is also reduced by resource multiplexing due to the on-demand buffer assignment at each output port. The proposed work results average network latency(16%) and average memory utilization (22%).
How to cite this article:
R. Anitha and P. Renuga. An Efficient Multi Port Network on Chip Router Architecture for Reliable Networks.
DOI: https://doi.org/10.36478/rjasci.2014.389.396
URL: https://www.makhillpublications.co/view-article/1815-932x/rjasci.2014.389.396