Asian Journal of Information Technology
ISSN: Online 1993-5994ISSN: Print 1682-3915
Abstract
Floating-Point (FP) multipliers are the key energy consumers in most of the present embedded processors based on digital signals and multimedia based appliances. A most common approach for reducing the energy utilization of FP multipliers is by cutting down the accuracy of FP multiplication operations under acceptable precision loss. This study proposes a multiple-precision FP multiplier to ably trade the energy utilization with the output quality. The proposed FP multiplier can perform low precision multiplication that generates 8, 14, 20 or 26 bit mantissa product through a hybrid technique that effectively fuses the row suppression and column suppression methodologies. Radix-8 Booth algorithm is used as the row suppression technique and truncation methodology is used for column suppression technique to tailor the output. Energy saving for this low precision multiplication is achieved by partly suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the mantissa’s bit width of the output product to change dynamically when it performs different FP multiplication operations to further decrease the energy consumption.
How to cite this article:
H. Mangalam and D. Gokila. Design of a Multi Precision Floating Point Multiplier Using a Hybrid Technique.
DOI: https://doi.org/10.36478/ajit.2016.3852.3857
URL: https://www.makhillpublications.co/view-article/1682-3915/ajit.2016.3852.3857