Asian Journal of Information Technology
ISSN: Online 1993-5994ISSN: Print 1682-3915
Abstract
Routers are playing crucial role in the field of networking. In this study, the multi port network on-chip router is proposed. The port weight based routing methodology is proposed in this study for low power applications. The proposed network architecture employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The proposed router does not maintain any routing table to route the packets from source to destination. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project navigator for synthesis purposes.
How to cite this article:
M. Deivakani and D. Shanthi. Performance Analysis of Low Power Port Bandwidth Weight Router Architecture.
DOI: https://doi.org/10.36478/ajit.2016.277.282
URL: https://www.makhillpublications.co/view-article/1682-3915/ajit.2016.277.282