Asian Journal of Information Technology
ISSN: Online 1993-5994ISSN: Print 1682-3915
Abstract
Presented here a new efficient pipeline FFT(Fast Fourier Transform) architecture based on the radix-2 4 algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-2 2 algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multipliers can enhance the area/power efficiency of the design. From synthesis simulations, the proposed complex constant multiplier achieved above 60% area reduction compared with the conventional programmable multiplier.
How to cite this article:
Jung-Yeol Oh , Kwang-Ho Chun and Myoung-Seob Lim . Low-Power Pipeline FFT Processor with Area-efficient Multipliers.
DOI: https://doi.org/10.36478/ajit.2005.768.772
URL: https://www.makhillpublications.co/view-article/1682-3915/ajit.2005.768.772