International Journal of System Signal Control and Engineering Application

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Design and Implementation of an Efficient FFT Processor using Modified Booth Multiplier

A. Manimaran, Aby K. Thomas and S.K. Sudheer
Page: 134-139 | Received 21 Sep 2022, Published online: 21 Sep 2022

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Abstract

The FFT plays an important role in OFDM regarding its performance. An efficient multiplier is needed to perform butterfly operation in FFT. This multiplier is related to area, power and time. The performance of OFDM depends upon the multiplier. The proposed multiplier is developed by using Verilog HDL and implemented by using Model Sim 6.3c for stimulation and Xilinx 12.4 for synthesis. The proposed multiplier reduce the number of slices, LTU (look up tables) and hence area and delay got reduced.

How to cite this article:

A. Manimaran, Aby K. Thomas and S.K. Sudheer. Design and Implementation of an Efficient FFT Processor using Modified Booth Multiplier.
DOI: https://doi.org/10.36478/ijssceapp.2017.134.139
URL: https://www.makhillpublications.co/view-article/1997-5422/ijssceapp.2017.134.139