Abstract

Buck-boost inverters found widespread applications in grid-connected systems, Uninterruptible Power Supplies (UPS) and other applications requiring voltage regulation above and below the output ac voltage. This study focuses on modeling of the working principles, computer simulation and design consideration of full bridge inverters. About 3 circuit configurations are described with various switching approaches and operation principles where comparison analysis between these circuits is conducted with respect to the output voltage, power, switch voltage and dissipated power. The simulation results stated that the proposed configuration of four-switch inverter with improved stability realized optimum output performances with reduced switching losses. Power electronic simulation platform (PSIM) and Matlab/Simulink platforms are used for simulating the circuit behaviors where applying both platforms in simulation process provides this study with additional tools in selecting the optimum circuit and results comparison.

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INTRODUCTION

In the past century, serious greenhouse effect and environmental pollution caused by overusing fossil fuels have disturbed the balance of global climate. High rate gas emissions mainly of CO₂ in the atmosphere have affected global surface temperatures which increase at a rate 0.6°C/century (Hodge, 2010; Chuang and Ke, 2008). Reducing the emissions of exhausted gases can be realized by using so called zero-emission renewable energy sources.

These sources have been rapidly developed in the past 2 decades mainly the applications of solar energy throughout using Photovoltaic (PV) cells which are clean, quiet and an efficient method for generating electricity. The PV power system has been widely used in power processing technologies such as solar power generation for grid connection; solar vehicle constriction, battery charger, water pump, satellite power system, traffic signals, electronic signs and so on (Bull, 2001; Rahman, 2003; Tseng et al., 2008). There are various electronics conversion systems and conversion topologies; one of these is called flyback based converters.

This kind converter found widespread applications due to its construction varieties starting from simple design to complicated design in additional to existing acceptable efficiency. Consequently, there are many research works on how to improve the efficiency of such converters (Hwu et al., 2008; Rouger et al., 2008; Weng and Xing, 2004; Lin et al., 2006; Jinno et al., 2003) for powering Light Emitted Diodes (LED) using high-efficiency flyback converter, fully integrated self driving converter, dual transformer, synchronous rectification and non-dissipated snubber circuits.

The resulting circuits are complicated due to the specific components required to drive the half-bridge switches in the active voltage clamping circuits. DC-DC and DC-AC converter circuits have huge configuration spectrum depending on the input/output requirements and operation condition (Hart, 2010; Kanaan and Al-Haddad, 2005; Jovcic, 2009). About three-switch flyback converter presents, one of most popular circuit due to simple design, acceptable efficiency and reduced number of components.

Here in after study proposes modified conversion circuit with various chopping switches aiming at realizing enhanced output performances and further elements reduction.

MATERIALS AND METHODS

Figure 1 shown Photovoltaic (PV) cells energized load circuit in both on-line and off-line grid connected mode where the PV cells/arrays can be connected directly to the inverter in daytime mode and charging the batteries while during the nighttime mode the batteries energized the load throughout the inverter circuit. This configuration has several merits such as reducing the battery operation time, better efficiency and better solar energy utilization. In the hereinafter descriptions, the PV source is described during the daytime operation and represented by two batteries with voltage of V_pv1 and V_pv2.

Circuit configurations: Several circuit configurations are discussed aiming at studying the behaviors of the output voltage, load current, boost current, transistor current, switching losses and output power. These circuits are:

•	Four-switch inverter configuration-circuit 1
•	Two-switch inverter configuration-circuit 2
•	Four-switch modified inverter configuration-circuit 3

Four-switch inverter configuration-circuit 1: Figure 2 shown single inverter with four transistorized switches built in PSIM environment where, the input voltage is supplied by PV panel and the output voltage is obtained by using Sinusoidal Pulse Width Modulation (SPWM) technique with purpose minimizing the voltage harmonics and ripples.

Principle of operation: About 2 operation modes can be described during single modulation period T_o as follows:

Fig. 1:	PV circuit with inverter energized grid/load connection

 

Fig. 2:	Four-switch inverter-circuit 1

 

Mode 1: Transistor switches Q₁ and Q₃ operates in complementary mode for positive half cycle of the output voltage while Q₂ and Q₄ operates for the negative half cycle. L_b1-b2 and C_b presents boost elements and C_o presents low-pass voltage filter. When Q₃ is switched on the inductor L_b1 accumulates the source voltage V_pv1 and the current oscillates with ringing frequency that depends on L_b1 and C_b. When Q₁ is switched on during the rest of the half modulation period T_o/2, the stored energy is transferred to the load. The equivalent circuits for both modes are shown on Fig. 3 and 4 while the obtained mathematical model is derived as follows:

Mathematical modeling: During the interval (0≤t≤D.T_o/2) where, Q₃ = on and Q₁ = off according to KVL, the voltage balance equations are:

(1)

Equation 1 in matrix form:

(2)

 

Fig. 3:	Circuit configuration for mode 1 a) circuit configuration b) the equivalent circuit when Q3 is switched on c) the equivalent circuit when Q1 is switched on

 

 

Fig. 4:	Circuit configuration for mode 2: a) circuit configuration; b) the equivalent circuit when Q4 is switched on and c) the equivalent circuit when Q1 is switched on

 

The boost current during this mode based on Eq. 2 is:

(3)

Where:

Where:

D	=	The duty cycle
To	=	The modulation period with chopping frequency fS, (To = 1/fS)

The transistor current i_Q3 (t) = i_b1 (t). During the interval (D.T_o/2<t≤T_o/2 where, Q₁ = on and Q₃ = off, the voltage balance equations according to this mode are:

(4)

Equation 4 in matrix form:

(5)

where, V_pv1, V_ccb′ (0) and Vc_o′ (0) are PV voltage and initial voltages of existing capacitors, respectively at t = D.T_o/2, R_L is the load resistance, L_b1 and L_b2 are the boost inductances and C_o is low-pass filter. For symmetrical circuit purposes usually L_b = L_b1 + L_o = L_b2 + L_o.. With purpose further simplification of the derived mathematical model, the capacitor charging current is negligible, therefore, the boost current flowing through the transistor Q₁ will be the load current i_o (t) = i_co (t)+ i_b1′ (t) i_b1′ (t) that can be expressed as:

(6)

Where:

δ	=	The damping factor
ωr	=	The angular velocity
S1, S2	=	The Laplace roots
Ico	=	The capacitor current
Ib1'	=	The boost current

(7)

Realizing over damping condition for the inverter current requires setting:

(8)

The initial current at I_b1' (0) can be determined by setting the current I_b1 (t₁ = DT_o/2) as follows:

(9)

The initial current I_b1(0) is determined from the inverter current flows in the circuit according to mode 2 at instant t₂ = T_o where the current will be:

(10)

The boundary conditions for current continuous mode can be determined from Eq. 10 by setting i_b1 (0) = i_b1 (T_o) = 0.

Mode 2: Transistor switches Q₂ and Q₄ operates in complementary mode for negative half cycle of the output voltage. The equivalent circuit for this mode is illustrated in Fig. 4. The derived equations for mode 1 are still valid for mode 2 whereas i_Q2 (t) = i_b1' (t) and i_o (t) = i_Q4 (t) = i_b1 (t) therefore, they will not be derived furthermore. The rms load voltage V_rms can be expressed as:

(11)

where, T_s is the period of inverted voltage. The transistor losses P_Q1, P_Q2, P_Q3 and P_Q4 can be expressed as follows:

(12)

where, V_Q1—on ,V_Q1-off, V_Q3—on, V_Q3-off, transistor voltge during on-state and off-state conduction respectively for Q₁ and Q₃, i_Q1-off, i_Q3-off are the transistor current during off-state conduction, respectively for Q₁ and Q₃. The load power expressed in rms value P_rms can be expressed as:

(13)

RESULTS AND DISCUSSION

Figure 2 shows that inverter is simulated using PSIM software and Matlab/Simulink platforms with circuit’s data shown in Table 1. The obtained simulation results are shown that Fig. 5 for both cases with and without boost capacitor C_b where, it is shown that existing of boost capacitor reshape the output voltage. While removing C_b by shorting it improves the shape of the output voltage and reduces the transistor losses as shown in Fig. 5c and d. The observed improvement is achieved on the expense of the low magnitude of this voltage and low output power as shown in Fig. 5e and f.

Improvement of the circuit performances: The main disadvantages are shown in Fig. 2, circuit are low output voltage with heavy harmonic content and high huge transistor losses therefore, overcoming these drawbacks can be achieved by proposing modified circuit operation mode with predetermined sequence as follows:

Mode 1: Q₁, Q₃ operates in complementary sequence while Q₂ is maintain in switched-on state.

Mode 2: Q₂, Q₄ operates in complementary sequence while Q₁ is maintain in switched-on state. The equivalent circuits of the modified operation are shown in Fig. 6 for 2 operation modes with time interval of D.T_o/2.

Mathematical modeling: During the interval (0≤t≤ D.T_o/2) where Q₃ = on, Q₁ = off and Q₂ = on, the boost current i_b1 (t) is the same as that expression derived in Eq. 3 therefore, i_Q1 (t) = i_b1'(t) and i_Q3(t) = i_b1 (t). While i_b2(t) has complicated character with expression:

(14)

Table 1:	Data specifications of simulated circuits

 

Fig. 5:	Inverter circuit waveforms: a) Circuit waveforms and b) Cb, c) Cb, d) Cb, e) Cb, f) Cb

 

 

Fig. 6:	Equivalent circuits of modification opertaion

 

Where:

(15)

For this mode, the transistor current i_Q2 (t) = i_b2 (t). During the interval (D.T_o/2≤t≤T_o/2) where Q₃ = off, Q₁ = on and Q₂ = on.

For simplification purposes when deriving the current equation, the effect of C_o and the initial values of the circuit currents are neglected therefore, the boost current can be expressed as follows:

(16)

where, V_pv = V_pv1 = V_pv2 is the PV voltage correspends to MPPT voltage. Figure 7 shows the simulation results of the operation sequence of inverter transistors, transistor current of Q₁ and Q₂, output voltage and current and load power. It is shown that the sinusoidal waveforms of the output voltage and current can be realized by connecting low-pass filter C_o across the load.

Fig. 7:	Modification circuit waveform: a) Transistors switching sequence; b) iQ1 and iQ2 without Co.; c) Output performances without Co.; d) Output performances with Co.

According to simulated results shows in Table 2 the effect of connecting both C_b and C_o cause significant increase in the load power up to 300% while the transistor looses increases to around 200% which justified the connection of such elements.

Fig. 8:	RMS output voltage of interver circuit 1: a) Output voltage Vrms -circuit1 and b) Transistor losses PQ1 circuit 1

 

Table 2:	Output performance of circuit 2

 

The output voltage of the inverter can be regulated by varying the duty cycle within safety operation limits (D_min≤D≤D_max).

Figure 8 shows the output voltage and transistor losses variation with respect to the modulation index M_a where it is shown that V_rsm and P_Q1 changes rapidly at low values of modulation index which destabilize the circuit operating. Furthermore, the minimum inverter voltage is the input PV voltage while D varies in the whole control range from 0-1 which gives this circuit more advantages comparing with the conventional inverter circuits.

Fig. 9:	Two-switch inverter-circuit 2

 

Fig. 10:	Main waveform of circuit 2

 

The main disadvantage of this circuit is the existing of high harmonic content in the transistor current which causes an excess of heat in these transistors.

Two-switch inverter configuration (circuit 2): Figure 9 shows two-switche inverter circuit with minimized number of circuit elements and simplified control circuit where the transistor's current i_Q1(t) = i_Q2(t) = i_b1(t) can be expressed as:

(17)

The output voltage and current are shown in Fig. 10 where, it is shown that despite the significant enhancement in the character of the output performances the transistor current I_Q1 still enough high to overheat the device and causes eventually damage.

Furthermore, the rapidly change of transistor voltage V_Q1 affects the transistor stability and may cause great tension on the transistor junctions and fast aging. Avoiding this, status can be achieved by proposing the circuit.

Fig. 11:	Four-switch modified inverter-circuit 3

Four-switch modofied inverter configuration with improved stability (circuit 3): Figure 11 shows such a circuit where the drawbacks of discussed in previous topic/circuit 2 are completely eliminated. The boost currents according to proposed configuration are as follows.

During the interval (0≤t≤D.T_o/2) where, Q₁ = off, Q₂ = on and Q₃ = on, the transistor current i_Q3 (t), boost current i_b1 (t) and i_Q2 (t) flows in the circuit can be expressed as:

(18)

Where:

(19)

During the interval (D.T_o/2≤t≤T_o/2) where Q₁ = on, Q₂ = on and Q₃ = off, the circuit currents are i_Q1' (t) and i_b1' (t) have the following expressions:

(20)

The obtained simulation results are shown in Fig. 12 where, it is shown that the load voltage and current have sinusoidal character, the transistor has stabilized parameters with respect to its voltage and current due to realized return current path leading to slightly change in switch status which in turn reduces the commutation voltage.

Fig. 12:	Main waveform of circuit 3: a) Output performances and b) Transistor voltage, current and losses

 

Table 3:	Output performance of circuit 3

 

Table 3 shows the main inverter output parameter and transistor losses where its shown that the effect of low-pass filter is negligible therefore, it can be removed with purpose reducing the circuit elements and avoiding capacitor rush currents. The Matlab/Simulink model and PWM control model of circuit 3 are shown in Fig. 13a, b while the main circuit waveforms and transistor voltage are shown in Fig. 13c, d.

Fig. 13:	Simulink results for circuit 3

Comparison analysis can be conducted between the 2 main circuits shown in Fig. 2 and 11 with respect to the output voltage, power and transistor switching parameters mainly transistor voltage, current and switching losses.

Table 4:	Comparison analysis

 

Fig. 14:	Simulink resulsts for circuit 1 and 3

 

Table 4 shows the obtained simulation results at modulation index of M_a = 0.8 while Fig. 14 shows the output voltage and transistor voltage for these circuits, respectively. The obtained simulation results according to Table 4 shows that maximum output power could be obtained when both boost and low-pass capacitors are added to the circuit. In this case the transistor must handle high blocking voltage.

Fig. 15:	Simulink results for circuit 1 and 3

On other hand, replacing C_b by boost inductor L_b reduces the rms output power in additional to significant decrease in the transistor blocking voltage. Figure 15 shows how the output voltage, transistor losses varies with respect to modulation index for both circuits where it is shown that the output voltage, transistor voltage and switching losses of circuit1 are greatly high comparing with that of circuit 3 therefore, circuit 3 presents optimized solution with respect to both transistor and output performances. Further, enhancement in the output performances can be achieved by using flyback-based inverter that combines bridge inverter with buck-boost converter. This approach is going to be described in future research.

CONCLUSION

Several circuit configurations have been studied with respect to the output voltage, load current, transistor current and losses where the following conclusion can be stated:

•	Mathematical model for the main circuit configuration (circuit1) is derived with assigned conditions for realizing continuous current mode
•	The combination of boost and low-pass filter in additional to propose switching sequence causes output voltage increase up to 70% but on the expense of high voltage across the switching devices in additional to observed high current ripples. Applying the configuration of circuit2 causes insignificant enhancement in the output performances
•	Avoiding the existence of high voltage across the device with reduced current ripples can be achieved by proposing the configuration of circuit 3 where the boost capacitor is replaced by boost inductor. In the mean time existing of such inductance limits the increase in the output voltage to be within 40%
•	The circuit stability and loss reduction are significantly enhanced according to the obtained results of circuit 3 built in Matlab/Simulink environment where the transistor voltage and yield losses are within the normal range
•	Further enhancement in the output performances can be achieved by applying modified PV buck-boost circuit in combination with flyback inverter. This task will be the object of future study

ACKNOWLEDGEMENTS

The researchers would like to thank the Open Society Institute (OSI) and USAID-AMEDEAST for fully sponsoring the visit to University of Hartford according to Palestinian Faculty Development Project (PFDP).

How to cite this article:

Sameer Khader. Modeling and Simulation of Various Inverter Circuits for Photovoltaic Applications.
DOI: https://doi.org/10.36478/ijepe.2011.74.83
URL: https://www.makhillpublications.co/view-article/1990-7958/ijepe.2011.74.83