Asian Journal of Information Technology

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Pulse Width Based CMOS Subcircuits for Voltage Mode Analog Neuron with 180 nm Technology

Mithila Ayyavoo and Vijayakumari Valsalam
Page: 114-118 | Received 21 Sep 2022, Published online: 21 Sep 2022

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Abstract

This study presents CMOS implementation of Voltage input to Pulse Converter (VPC) and activation function circuits in 180nm technology using PWM technique. The CMOS circuits are built with ±1.8 V supply. The circuits designed are reliably used in input or hidden layers of neural network. The pulsed output from VPC can be given as input to synapse multiplier along with activation function that uses PWM signals to compute. These subcircuits are of immense importance when an overall design goal is CMOS Multilayer Perceptron (MLP) design with PWM technique. The performance parameters are simulated and observed using cadence spectre Virtuoso 6.1.6 BSIM3v3.

How to cite this article:

Mithila Ayyavoo and Vijayakumari Valsalam. Pulse Width Based CMOS Subcircuits for Voltage Mode Analog Neuron with 180 nm Technology.
DOI: https://doi.org/10.36478/ajit.2018.114.118
URL: https://www.makhillpublications.co/view-article/1682-3915/ajit.2018.114.118