Asian Journal of Information Technology

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An Analog Low Power VLSI Implementation of Artificial Neural Network Architecture

N. Rajeswaran and S. Arumugam
Page: 955-960 | Received 21 Sep 2022, Published online: 21 Sep 2022

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Abstract

All the modern technologies in digital systems are slowly converting in to the analog implementation especially, for the fault tolerance and low power consumption. But, the analog implementation of parallel computation with ANN (Artificial Neural Network) in real time implementation is not an easy task in all aspects. This study mainly focuses on the implementation of Neural Network Architecture (NNA) with on chip learning in analog VLSI (Very Large Scale Integration). Back Propagation Neural network (BPN) algorithm is designed and simulated in analog domain by using tanner EDA tool.

How to cite this article:

N. Rajeswaran and S. Arumugam. An Analog Low Power VLSI Implementation of Artificial Neural Network Architecture.
DOI: https://doi.org/10.36478/ajit.2016.955.960
URL: https://www.makhillpublications.co/view-article/1682-3915/ajit.2016.955.960