Asian Journal of Information Technology
ISSN: Online 1993-5994ISSN: Print 1682-3915
Abstract
Full adder is the basic building blocks for various arithmetic circuits such as carry select adder, array multipliers, ripple carry adder, high speed adder, parallel adder and so on. In order to improve the performance of the digital computer systems one must improve the basic full adder cell. The proposed full adder design by using Gate Diffusion Input/Index (GDI) technique reduces the power consumption with less transistor count while maintaining less interconnection nodes of logic design, when compared with existing full adder designs such as complementary pass transistor logic, standard CMOS logic, transmission gate logic and transmission function adder logic. The simulation was carried out on TSMC HSPICE 180 nm technology. The simulation result shows that the design has more efficient with less area, less power consumption and as compared to existing hybrid full adder techniques.
How to cite this article:
Dhandapani Samiappan and R. Srinivasan. Low Power and Area Efficient Full Adder Design Using GDI Technique.
DOI: https://doi.org/10.36478/ajit.2016.750.755
URL: https://www.makhillpublications.co/view-article/1682-3915/ajit.2016.750.755