Asian Journal of Information Technology
ISSN: Online 1993-5994ISSN: Print 1682-3915
Abstract
Interpolation is a technique which is used to enhance or reduce the size of digital images to correct spatial distortion. In convolution based interpolation scheme, the quality of the scaled image depends upon the order of convolution kernel. A better quality of interpolation can be achieved by using higher order models but it requires complex computation and heavy memory access time. Fast First Order Polynomial Convolution Interpolation Method is one of the efficient methods for scaling images still there exists complexity in generating weights. This study presents an area efficient Weighting Coefficient Generation (WCG) circuit for digital image scaling. In the proposed hardware architecture, the WCG circuit has decreased the hardware complexity substantially. It includes only nine arithmetic components which is much less than the number of components in the existing hardware architecture of WCG of Fast First Order Polynomial Convolution Interpolation (FFOPCI) algorithm. The computational burden is less when using the proposed architecture for generating the weighting coefficients in FFOPCI algorithm. Thus, high quality scaled images can be obtained with low computational burden when using the proposed architecture in FFOPCI algorithm.
How to cite this article:
C. John Moses and D. Selvathi. An Area Efficient Weighting Coefficient Generation Architecture for Polynomial Convolution Interpolation.
DOI: https://doi.org/10.36478/ajit.2014.291.299
URL: https://www.makhillpublications.co/view-article/1682-3915/ajit.2014.291.299