TY  - JOUR
T1  - Design and Implementation of an Efficient FFT Processor using Modified Booth Multiplier
AU - Manimaran, A. AU - K. Thomas, Aby AU - Sudheer, S.K. 
JO  - International Journal of System Signal Control and Engineering Application
VL  - 10
IS  - 5
SP  - 134
EP  - 139
PY  - 2017
DA  - 2001/08/19
SN  - 1997-5422
DO  - ijssceapp.2017.134.139
UR  - https://makhillpublications.co/view-article.php?doi=ijssceapp.2017.134.139
KW  - CSLA
KW  -modified booth
KW  -slices
KW  -LUT (look up tables)
KW  -delays
KW  -PPG
AB  - The FFT plays an important role in OFDM
regarding its performance. An efficient multiplier is
needed to perform butterfly operation in FFT. This
multiplier is related to area, power and time. The
performance of OFDM depends upon the multiplier. The
proposed multiplier is developed by using Verilog HDL
and implemented by using Model Sim 6.3c for stimulation
and Xilinx 12.4 for synthesis. The proposed multiplier
reduce the number of slices, LTU (look up tables) and
hence area and delay got reduced.
ER  -