TY  - JOUR
T1  - On Ways to Improve Adaptive Adjoint LMS Algorithm Using High Speed Architecture
AU - , N.J.R. Muniraj AU - , R.S.D. Wahidhabanu 
JO  - International Journal of Electrical and Power Engineering
VL  - 1
IS  - 3
SP  - 260
EP  - 263
PY  - 2007
DA  - 2001/08/19
SN  - 1990-7958
DO  - ijepe.2007.260.263
UR  - https://makhillpublications.co/view-article.php?doi=ijepe.2007.260.263
KW  - Adaptivefilters
KW  -adjointlms
KW  -filtered-XLMS
KW  -floorplanning
KW  -FPGA
AB  - This study proposes a technique termed Adjoint LMS which provides a simple alternative to the other adaptive algorithms. Here we implement Adjoint LMS algorithm into VLSI using Verilog HDL. This ASIC chip is designed, simulated and synthesized using Xilinx FPGA Virtex 2P(2vp30ff896-6) and the workability of the algorithm is tested for noise cancellation and verified using matlab.
ER  -