TY  - JOUR
T1  - Performance Analysis of EMTCMOS Technique Based D Flip Flop Design at Varied Supply
Voltages and Distinct Submicron Technology
AU - Sreenivasulu, P. AU - Srinivasa Rao, K. AU - Vinaya Babu, A. 
JO  - International Journal of Soft Computing
VL  - 15
IS  - 5
SP  - 119
EP  - 127
PY  - 2020
DA  - 2001/08/19
SN  - 1816-9503
DO  - ijscomp.2020.119.127
UR  - https://makhillpublications.co/view-article.php?doi=ijscomp.2020.119.127
KW  - Power consumption
KW  -D flip flop
KW  -EMTCMOS
KW  -scaling
KW  -leakage current and delay
AB  - Power is a major concern in the design and
implementation of sequential circuits. Various attempts
were made in the past to optimize power consumption
values in the sequential circuits such as flip flops.
Enhanced multi threshold CMOS is adopted in this work,
which yielded best results for D flip-flop in terms of
power consumption. The results are also examined for
180, 90 and 45 nm technology and the performance of the
circuit is analyzed. A comprehensive analysis is carried
out in terms of performance parameters as power
consumption, leakage current and delay. The EMTCMOS
Flip Flop is also used to design the ripple counter circuit
and the performance was analyzed. However, this design
is analyzed for only 90 nm technology. This research is
carried on Cadence Virtuoso tool at 180, 90 and 45 nm
technology.
ER  -