TY  - JOUR
T1  - Hardware Complexity Reduction of Parallel FIR Filter Structures Based on Fast FIR Algorithm
AU - Shanmugaraj, G. AU - Kalaiarasi, N. 
JO  - International Journal of Soft Computing
VL  - 9
IS  - 5
SP  - 308
EP  - 313
PY  - 2014
DA  - 2001/08/19
SN  - 1816-9503
DO  - ijscomp.2014.308.313
UR  - https://makhillpublications.co/view-article.php?doi=ijscomp.2014.308.313
KW  - Hardware complexity
KW  -symmetric coefficients
KW  -Finite Impulse Response (FIR)
KW  -sub-filter
KW  -odd
AB  - The main objective of the study is to reduce the hardware 
  cost considerably. Parallel Finite Impulse Response (FIR) filters can be implemented 
  with less hardware cost at different level of parallelism using Fast Symmetric 
  Convolution algorithm. Multiplications are major part in FIR filter implementation. 
  The number of required multipliers is reduced by effectively cascading the short 
  length FIR filter using symmetric coefficients in the sub-filter section. The 
  reduction of multipliers and adders are more advantages in terms of silicon 
  area. For example, the proposed structure of a four-parallel 144-tap FIR filter 
  saves 33 multipliers and 7 adders whereas for a eight-parallel 576-tap FIR filter 
  saves 351 multipliers and 11 adders. Finally, when the length of filter is large, 
  the proposed parallel FIR filter structure saves the hardware cost in terms 
  of multiplications in both odd and even length.
ER  -