TY  - JOUR
T1  - ASIC Implementation of Low Power Area Efficient Folded Binary Comparator
AU - Saravanakumar, N. AU - Kumari, G.E. Kanya AU - Nandhakumar, A. AU - NirmalKumar, A. 
JO  - International Journal of Soft Computing
VL  - 9
IS  - 5
SP  - 298
EP  - 302
PY  - 2014
DA  - 2001/08/19
SN  - 1816-9503
DO  - ijscomp.2014.298.302
UR  - https://makhillpublications.co/view-article.php?doi=ijscomp.2014.298.302
KW  - priority encoding
KW  -carry look ahead
KW  -tree structure
KW  -digital arithmetic
KW  -Binary comparator
AB  - ASIC implementation of a parallel binary comparator based 
  on radix-2 tree structure, utilizing Carry Look Ahead (CLA) technique is proposed 
  in this study. This novel comparator architecture achieves both low power and 
  high-speed operation, particularly at low-input data activity environments. 
  The proposed comparator is designed using VHDL code and synthesized using ALTERA 
  QUARTUS-II. Experimental evaluation of the proposed and state of the art designs 
  revealed that the proposed comparator design exhibits a reduction in delay by 
  49.8% and gate count by 42.6% for a 16 bit design, compared to the best of the 
  schemes used for comparison.
ER  -