TY  - JOUR
T1  - Reusable Network on Chip Design
AU - Arun Kumar, P. AU - Pandian, P. AU - Perinbham, Raja Paul 
JO  - International Journal of Soft Computing
VL  - 9
IS  - 4
SP  - 235
EP  - 239
PY  - 2014
DA  - 2001/08/19
SN  - 1816-9503
DO  - ijscomp.2014.235.239
UR  - https://makhillpublications.co/view-article.php?doi=ijscomp.2014.235.239
KW  - Fault tolerant design
KW  -network on chips
KW  -routing table
KW  -model
KW  -path
AB  - Researchers present a Fault Tolerant Hardware Routing Model 
  using reusability technique for the Network on Chips (NOC) during faulty conditions 
  to enable the router to transmit the packets effectively without any loss. The 
  network has been designed for 3x3 and 4x4. The faults are mainly injected due 
  to transients in the real world which affects the routing path and they are 
  modeled as digital faults. The reliability of the design has been found out 
  to be 100% for bidirectional design of NOC routers at a frequency of 500 MHz.
ER  -