TY  - JOUR
T1  - Design and Implementation of LMS Adaptive FIR Filter Based on
OBC Distributed Arithmetic Algorithm with MCSLA
AU - Kalaiyarasi, D. AU - Kalpalatha Reddy, T. 
JO  - Journal of Engineering and Applied Sciences
VL  - 14
IS  - 20
SP  - 7756
EP  - 7764
PY  - 2019
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2019.7756.7764
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2019.7756.7764
KW  - Least Mean Square (LMS) adaptive filter
KW  -Distributed Arithmetic (DA)
KW  -Modified Carry Select
Adder (MCSLA)
KW  -Shift accumulate
KW  -Offset Binary Coding (OBC)
KW  -Lookup Tables (LUTs)
AB  - Distributed Arithmetic (DA) is a methodology used to save resources in MACs implementing DSP
functions. Without using multipliers, DA has been computing the multiply-accumulate process. In conventional
DA, the partial products of the filter coefficients have been pre-computed and stored in parallel Lookup Tables
(LUTs). The results of parallel LUTs have been given to Carry Select Adder (CSLA) with the help of multiplexer.
The sizes of the hardware multiply accumulate has been reduced in DA based adaptive filter which is well suited
to FPGA design. It also reduces the number of logic elements in the design. In the proposed method, OBC
based DA in LMS adaptive filter has been implemented to reduce the half of the logic elements when compared
to the conventional DA. Offset Binary Coding (OBC) is a digital coding scheme where all-zero corresponds to
the minimal negative value and all-one to the maximal positive value. Nothing but logic elements but also, the
power and time have been reduced over the conventional method. The main concern of the proposed method
is the throughput. Throughput is defined as the total clock rates by the number of clock cycles needed for
filtering and updating of filter coefficients. The proposed architecture has been implemented in Quartus II
9.1 sp 1 Web Edition with the device as Stratix-EP2S15F484C3. The proposed architecture for length N = 16
achieves 14.4% in DATs, 44.26% in No. of logic elements, 46.57% in No. of registers and 2.25% in power.
Likewise, the proposed architecture for length N = 32 offers 4.28% in DATs, 70.6% in No. of logic elements,
71.93% in No. of registers and 6.5% reduction in power consumption.
ER  -