TY  - JOUR
T1  - Capacitance-Toggle Rate Weighting to Optimize Switching Power at Placement Stage of VLSI Conception
AU - Darmi, Mohammed AU - Cherif, Lekbir AU - Benallal, Jalal AU - Elgouri, Rachid AU - Hmina, Nabil 
JO  - Journal of Engineering and Applied Sciences
VL  - 14
IS  - 10
SP  - 3243
EP  - 3249
PY  - 2019
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2019.3243.3249
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2019.3243.3249
KW  - Low power
KW  -physical design
KW  -placement
KW  -power optimization
KW  -dynamic power
KW  -switching activity
KW  -performance
AB  - Power consumption is one of the major criteria of an Integrated Circuit (IC) and becomes more
important than performance and surface in some applications. Therefore, it is necessary to find new techniques
to reduce the power consumed by an IC. This study presents two power-aware techniques: Toggle rate and
capacitance-toggle rate weighting which aims to reduce the switching power of nets at the placement stage.
These techniques drive the placement engine to reduce the wire length of critical power nets by placing their
relative cells close to each other. For an optimal solution, the weighting is applied only on power critical nets
that consume more than 80% of the total power in the connection. Experimental results on nine IC industrial
designs show an average improvement of 11.8% in total net power and 3.7% of total consumed power.
ER  -