TY  - JOUR
T1  - Design and Verification of Asynchronous FIFO with Novel Architecture Using
Verilog HDL
AU - Yadlapati, Avinash AU - Kakarla, Hari Kishore 
JO  - Journal of Engineering and Applied Sciences
VL  - 14
IS  - 1
SP  - 159
EP  - 163
PY  - 2019
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2019.159.163
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2019.159.163
KW  - synchronization
KW  -FIFO
full
KW  -flags
KW  -write pointer
KW  -read pointer
KW  -Asynchronous FIFO
KW  -gray code converter
KW  -FIFO empty
KW  -memory queue
AB  - A FIFO is a “First In First Out” memory queue between any two asynchronous domains with
simultaneous write and read access to and from the FIFO, these accesses being on different clocks. The FIFO
has input ports like data input (write), write clock, read clock, reset and output ports like FIFO full flag, data out
(read) and FIFO empty flag. It also has control signals like write enable and read enable. The most important
signals that control the FIFO operation are the write pointer and the read pointer. These pointers in the case
of Synchronous FIFO operate in a single clock while in the case of Asynchronous FIFO operate in two clocks,
write clock and read clock respectively. FIFO can be either Synchronous or Asynchronous. The basic difference
between them is that the entire operation of Synchronous FIFO is entirely dependent on the clock whereas the
write operation and read operation of Asynchronous FIFO are asynchronous to each other. In this study a
Novel approach to designing an Asynchronous FIFO is used. Instead of taking a separate bit to identify
whether the FIFO is full or empty, the resaerchers have used an internal signal (last operation) to identify if the
FIFO is full or empty.
ER  -