TY  - JOUR
T1  - Novel Eleven-Transistor (11T) SRAM for Low Power Consumption
AU - Prabhu, C.M.R. AU - Nair, D. Sharmila Devi AU - Babu, S. Kishen AU - Chockalingam, P. 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 17
SP  - 7256
EP  - 7259
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.7256.7259
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.7256.7259
KW  - SRAM
KW  -power consumption
KW  -access time
KW  -read/write
KW  -SNM
KW  -worse
AB  - Low power SRAM array is fundamental to organize substantial reliability and prolonged battery life
for portable application. Since, charging/discharging enormous bit lines capacitance consume large portion of
power, new SRAM design is proposed to lessen the power consumption and access delay for read/write
operation. The proposed 11T cell contains two transistors in the feedback path of the respective inverter to
minimize the write power consumption. Cell is simulated in terms of speed, power and stability. The simulated
results show that the read and write power of the 11T SRAM cell is reduced up to 49 and 80% at 0.7 V,
respectively and cell achieves 2.5× higher Static Noise Margin (SNM) compared to the conventional 6T SRAM
cell. The designed cell can be utilized in mobile appliances even in worse temperature state with lower power
consumption.
ER  -