TY  - JOUR
T1  - Routing Architecture for Efficient Network on Chip Using Agent
AU - Ajay Kumar, Y.L. AU - Satyanarayana, D. AU - Vishnu Vardhan, D. 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 15
SP  - 6002
EP  - 6007
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.6002.6007
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.6002.6007
KW  - NOC
KW  -packet injection
KW  -data integrity
KW  -processing element
KW  -routing agents
KW  -routing efficiency
AB  - Network-on-chip is one of the promising computing paradigms. Continuing research is carried out
to improve the architecture and performance of networking techniques on the chip. In this research, we will
demonstrate that routing efficiency can be improved in a mesh network using inbuilt "Agents" inside the
processing elements. Moreover, this architecture is convenient to be used in either homogeneous or
heterogeneous mesh networks. The packets are injected into various processing elements thorough multiple
ports. The packet frame is designed and managed in such a way that keeping track of processed and
un-processed objects is easy to track and helps maintain data integrity. We see that implementation results on
FPGA show better area performance, minimized routing complexity and better throughput in a processing
element.
ER  -