TY  - JOUR
T1  - 2D Symmetric16×8 SRAM with Reset
AU - Basha, D. Khalandar AU - Reddy, Shashikanth AU - Aruna Manjusha, K. 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 1
SP  - 58
EP  - 63
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.58.63
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.58.63
KW  - SRAM
KW  -body biasing
KW  -multi bit SRAM
KW  -portability
KW  -transistors
KW  -specification
AB  - SRAM is one of the basic element used in memory. Large memories are needed as more amount of
information to store in today’s life. The on-chip memory is increasing for every generations of processors and
systems. In VLSI design metrics are area, cost, portability, speed and power. To meet specification many
topologies are existing for basic SRAM cell design. In this study basic 6T SRAM is considered for which
additional transistors are added to reset the memory using reset pin. The back to back inverter circuit of SRAM
is driven on both sides. For this circuit two additional transistors are added to enable based on row-sel and
coln-sel inputs. To increase the speed of operation of the circuit additional circuit gate level body biasing
circuit. This modified basic SRAM cell is used to design for 16×1 SRAM memory later extended for 16×8
memory. The circuit is designed with GPDK45 and simulated by cadence spectre simulator.
ER  -