TY  - JOUR
T1  - DVCR: Diagonal Virtual Channel NoC Router Architecture for Multiprocessors
AU - Prasad, E. Lakshmi AU - Reddy, A.R. AU - Prasad, M.N. Giri 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 10
SP  - 3562
EP  - 3566
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.3562.3566
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.3562.3566
KW  - System on chip
KW  -network on chip
KW  -multiprocessors
KW  -router architecture
KW  -multiprocessor
KW  -destination
AB  - Network on chip is a modern architecture for multiprocessor. Due to the complex routing in Network
on Chip (NoC), it is obstructed with the issue of latency, deadlock and traffic congestion. The problem of
deadlock and traffic congestion can be managed by the proposed method called as Diagonal Virtual Channel
Router (DVCR) design. Low latency XY routing algorithm can reduce latency to reach the critical path
destination node in NoC. Therefore, DVCR and XYD routing algorithm can manage the congestion and latency
can be reduced by 50% when compared to existing methods. These methods are examined for 4×4 2-D MESH
and 2-D TORUS. Experimental research carried out by using Xilinx 14.7 and targeted on the Vertex-7 FPGA. As
per the synthesis report, the minimum amount of time period to reach the critical path node in 2D-mesh
is 5.548 nsec and for 2D-Torus is 5.507 nsec, so, each router can execute in four clock cycles, therefore, overall
critical path distance node in 2D-mesh is 16.644 nsec and in 2D torus is 11.014 nsec. Low latency applications
for NoC based MPSoCs.
ER  -