TY  - JOUR
T1  - Design and Implementation of Low Power Clock Gating
Technique in 16 bit ALU Circuit
AU - Shakor Mogheer, Hussein AU - Saleh, Adham Hadi AU - Hameed, Abbas Salman 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 9
SP  - 2767
EP  - 2772
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.2767.2772
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.2767.2772
KW  - arithmetic
KW  -clock power
KW  -dynamic power
KW  -power dissipation
KW  -Clock gating
KW  -verified
KW  -addition
AB  - Power dissipation is the most important issues faced all the designers in modern science. Moreover,
a clock pulse is a main reason of power consumption in digital design. Moreover, clock gating method in
structure stage can be executed to decrease dynamic power. This study aim to design, implement and compare
the various resources consumption utilizing clock gating techniques in 16 bit ALU design. The two clock
signals proposed and used in the normal ALU design. Which supply the clock signal for one block only either
logical or arithmetic block, while the other is switch OFF. With the purpose of executing arithmetic and logic
architecture, 130 nm standard cell technology libraries are employed to realize the implementation. In addition,
the simulations are compiled by using the Modelsim Software. Verilog Hardware Description Language (HDL)
models is verified the construction of arithmetic and logic process. Similarly, it carried out with Quartus II 14.1
web edition (64 bit). This technique leads to the reduction in dynamic power consumption using AND based
clock gating up to 32.88%. Therefore, the proposed design is acceptable to usage in the system to optimize
power consumption in modern devices.
ER  -