TY  - JOUR
T1  - An FPGA Implementation of the Serpent Algorithm using Xilinx System Generator
AU - Al-Gailani, M.F. 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 8
SP  - 1974
EP  - 1979
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.1974.1979
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.1974.1979
KW  - FPGA
KW  -Serpent cipher
KW  -SP-network
KW  -throughput
KW  -TPS
KW  -design
AB  - Serpent cipher had been designed as an alternative for the previous encryption standard algorithm,
the data encryption standard. It had been chosen within the shortlist by the National Institute of Standard and
Technology which eventually selected Rijndael cipher as an Advanced Encryption Standard. There is no doubt
on the security of Serpent, however because of the high number of rounds it has slower implementation speed
compared to the chosen algorithm. All over, it is important to design an efficient hardware implementation for
a well-known algorithm as an option in case the current standard is being attacked. This study presents an
FPGA implementation of the Serpent algorithm, the design is focused on the area rather than throughput thus
iterative looping architecture is suggested. It is implemented on the target device Xilinx Virtex-6
xc6vlx195t-3ff1156 using ISE design suite 14.7. The design achieved a maximum frequency of 111.757 MHz
providing 0.447 Gbit/sec of throughput.
ER  -