TY  - JOUR
T1  - Analysis of DCVS and MODL Logic in CLA
AU - Kandasamy, Nehru AU - Naidu, Utlapalli Soma AU - Telagam, L. Shruthi Nagarjuna 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 7
SP  - 1844
EP  - 1850
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.1844.1850
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.1844.1850
KW  - low power VLSI
KW  -DCVS
KW  -MODL
KW  -MCC
KW  -CLA
KW  -CMOS logic
AB  - This study deals about 4 bit carry look ahead adder implementation in differential cascade voltage
switch and multi output domino logic styles. The main idea of Manchester carry chain is splitting the carry into
odd and even parts for reducing the delay time for carry bit to increase the speed of the circuit. The DCVS and
MODL logic styles are analyzed in terms of power, delay and power delay product with supply
voltages 0.8-1.8 V and temperature 27°C at 180 nm technology.
ER  -