TY  - JOUR
T1  - Design and Implementation of a Complex Binary Adder
AU - Jamil, Tariq AU - Medhat Awadalla, H. AU - Mohammad, Iftaquaruddin 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 7
SP  - 1813
EP  - 1828
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.1813.1828
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.1813.1828
KW  - Binary complex numbers
KW  -FPGA
KW  -complex binary adder
KW  -Logism Software
KW  -microprocessors
KW  -utilizing
AB  - To represent complex number as single-unit binary number, a complex binary number utilizing base
(-1+j) has been proposed in the scientific literature. In this study, we have designed a nibble-size adder based
on this number system using the traditional truth table/Kmap approach and implemented it on Xilinx Virtex
FPGAs. We have compared this design with the minimum-delay nibble-size complex binary adders and base-2
binary adders designed using decoder and ripple-carry principle. This research work leads us to the conclusion
that the complex binary is a viable number system for designing Arithmetic and Logic Unit (ALU) of today’s
microprocessors.
ER  -