TY  - JOUR
T1  - Design and Implementation of a Low-Voltage Four Selectable Fractional-Order
Differentiator in a 0.35 μm CMOS Technology
AU - C. Abad, Alexander AU - L. Abulencia, Geoffrey AU - Yap, Roderick AU - A. Gonzalez, Emmanuel 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 6
SP  - 1479
EP  - 1486
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.1479.1486
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.1479.1486
KW  - Constant phase element
KW  -resistor-capacitor ladder
KW  -selectable fractional-order differentiator
KW  -characterization
KW  -implementation
KW  -microcontroller
AB  - This study focused on the design and implementation of a four selectable Fractional-Order (0.2, 0.4,
0.6 and 0.8) Differentiator (FOD) in a 0.35 μm CMOS technology operated at 1.5 V supply. In comparison with
previous research that use discrete components and generic microcontroller to switch an FOD from one order
to the next, this design of a selectable FOD was realized in an analog microelectronics scale. The dimension of
the Integrated Circuit (IC) layout was further reduced by employing reusability of capacitors and resistors. The
whole chip layout of the design, excluding input/output pads has a dimension of 8.10×6.30 mm or equivalent
to a final area of 51.03 mm<sup>2</sup>. The four possible orders of an FOD were characterized in terms of its magnitude and
phase response in the working bandwidth from 10-1 kHz. Characterization was made using SPICE simulation
tool and IC layout editor software.
ER  -