TY  - JOUR
T1  - Enhanced Launch-Off-Capture Testing Using BIST Designs
AU - Bharadwaj, Meka AU - Kishore, Hari 
JO  - Journal of Engineering and Applied Sciences
VL  - 12
IS  - 3
SP  - 636
EP  - 643
PY  - 2017
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2017.636.643
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2017.636.643
KW  - BIST
KW  -LOS
KW  -LOC
KW  -ELOC
KW  -testing
KW  -Xilinx
AB  - Now a days chip designing has become more and more complex and then the transistor size had been
decreased to nanometre level. The designing of the chip is taking so long and to test, it would take many more
years. So, in order to decrease the testing time circuit is made to test itself making it possible to self test which
is built inside the chip. Built in self test is design which can test itself and reduce the testing time. But, there
are many more difficulties in continuing the processes. One among is the transition fault. Here, we present an
idea to overcome the transition fault in the bist by using the fault generation of the transition pattern methods.
They are LOC (Launch Off Capture) and LOS (launch off shift) methods. And also, we are implementing the
enhanced launch off capture method in the bist. Work is done by the Xilinx 14.5 Version.
ER  -