TY  - JOUR
T1  - Performance Evaluation of Parallel Multipliers
AU - Ravinder, T. AU - Siridhara, A.L. AU - Vucha, Mahendra 
JO  - Journal of Engineering and Applied Sciences
VL  - 12
IS  - 20
SP  - 5186
EP  - 5189
PY  - 2017
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2017.5186.5189
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2017.5186.5189
KW  - Arithmetic logic unit
KW  -Digital Signal Processing (DSP)
KW  -Serial Parallel Multiplier (SPM)
KW  -Multiply and Accumulate Unit (MAC)
KW  -multimedia applications
KW  -computing architectures
AB  - Now a days multimedia applications are demanding high speed computing architectures. Adders and
multipliers are very important functional blocks in Arithmetic and Logic Unit (ALU) of high speed computing
architectures. For computing systems fast multiplication is always a significant requirement for high
performance. This study presents the implementations of the high speed multipliers and their comparative
analysis. In this study, we have proposed VLSI architecture for widely used parallel multipliers such as Booth’s
multiplier, Wallace multiplier and Dadda tree multipliers in order to acquire their design attributes like speed,
area. The acquired design parameters of the multipliers can be analyzed to design optimum speed Multiply and
Accumulate (MAC) unit used for multimedia applications like filters, synthesizers, wireless communication
channels, etc.
ER  -