TY  - JOUR
T1  - Reversible Realization of Common Bus Structure for ALU Applications
AU - Shukla, Vandana AU - Singh, O.P. AU - Mishra, G.R. AU - Tiwari, R.K. 
JO  - Journal of Engineering and Applied Sciences
VL  - 12
IS  - 11
SP  - 2984
EP  - 2989
PY  - 2017
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2017.2984.2989
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2017.2984.2989
KW  - Common bus structure
KW  -VSMT gate
KW  -Sayem gate
KW  -reversible realization of digital circuits
KW  -nature
KW  -apporach
AB  - Growth of research in the field of effective digital computing systems leads to the need of efficient
digital design approaches. Reversible logic concept is the result of this necessity. This design approach creates
low power efficient digital circuits with improved performance. In the CPU/ALU bus provides the path for data
flow and covers major area of the CPU. As the conventional buses are irreversible in nature when data flows
through these buses it consumes power and additional hardware is required to sink the generated heat.
Moreover by designing a bus using reversible technology power requirement is decreased with the removal
of need of heat sink. In this study, we focus upon the designing of common bus structure using reversible logic
approach. Common bus structure provides an effective way to provide the facility of communication between
computer subsystems. The proposed approach for reversible realization of common bus system is simulated
and synthesized for ModelSim simulator and Xilinx Software, respectively.
ER  -