TY  - JOUR
T1  - Proposed System Architecture for Integrity Verification of Embedded Systems
AU - Ali A. Al-Wosabi, Abdo AU - Shukur, Zarina 
JO  - Journal of Engineering and Applied Sciences
VL  - 12
IS  - 9
SP  - 2371
EP  - 2376
PY  - 2017
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2017.2371.2376
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2017.2371.2376
KW  - Embedded systems
KW  -software tampering
KW  -system integrity
KW  -integrity verification
KW  -computed hash value
AB  - Since, the digital devices play essential roles in our daily life, system integrity is important. Thus,
there is a need to propose appropriate and effective techniques/tools to verify that the original/pure Embedded
Systems (ESs) have been used in those devices. We present our proposed system architecture for ESs integrity
verification which includes two main phases: fetching an ES code at a server site (i.e., data center) and
examining the ES at a remote site (using a designed user application). The integrity of that ES could be verified
by comparing the computed hash value, result could show whether that system has been altered or tampered
with. We integrate hash function (SHA-2) with a random key to calculate a unique digest value for a targeted
system. Also, we use timestamps and nonce values, two secure keys and public key algorithm to design a
security protocol.
ER  -