TY  - JOUR
T1  - Design of a Three-Phase Buck-Type PFC PWM Rectifier
AU - Peeterson, E. Jose AU - Raja, J. Emerson AU - Hossen, J. AU - Efzan, M.N. Ervina AU - Velrajkumar, P. 
JO  - Journal of Engineering and Applied Sciences
VL  - 12
IS  - 4
SP  - 1040
EP  - 1049
PY  - 2017
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2017.1040.1049
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2017.1040.1049
KW  - SLO
KW  -THD
KW  -DC current
KW  -AC supply
KW  -voltage
AB  - This study presents the design of a three-phase buck-type PFC PWM rectifier simulation to step down 7.5 KVA, 400 V line-to-line AC to form a 380 V DC bus. Low power version of the buck rectifier is also implemented in hardware. The buck rectifier circuit topology is adopted by modifying the commonly known current source rectifier. A SVPWM technique called Switching Loss Optimized (SLO) modulation is employed to easily control the rectifier and carryout power factor correction. An input AC filter is designed to reduce THD and at the same time achieve a high leading power factor. An output DC filter is also designed to provide ripple-free constant DC current and voltage. Closed loop control is applied to maintain steady output voltage in the event of disturbances in the AC supply or the load. The circuit is first designed to meet the specifications and then tested using Simulink/Matlab. The finalized design from the simulation is verified by low power hardware implementation.
ER  -