TY  - JOUR
T1  - FPGA Hardware Implementation for Accelerating QR Decoding
AU - Alhammami, Muhammad AU - Nyeancheong, Soon AU - Tan, Wooi-Haw AU - Ooi, Chee Pun 
JO  - Journal of Engineering and Applied Sciences
VL  - 11
IS  - 14
SP  - 3273
EP  - 3278
PY  - 2016
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2016.3273.3278
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2016.3273.3278
KW  - hardware implementation
KW  -demandhigh-performance
KW  -FPGA
KW  -QR decoding
KW  -QR code
AB  - QR codes has gained more attention as an input interface to many embedded applications. However,
some applications need extra computing resources which demandhigh-performance QR code decoder. This
study suggests a hardware solution to accelerate the decoding function. The proposed design is implemented
using CYCLON II FPGA from Altera with the decoded results display on a LCD. The initial experiments show
that it is possible to decode the unmasked QR raw bits efficiently in real time which shows good potential to
offload the computationally intensive task of QR image decoding process from the main processor and to room
for advanced image pre-processing and security decryption algorithm to be implemented in FPGA.
ER  -