TY  - JOUR
T1  - Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process
AU - Murali, A. AU - Kishore, K. Hari AU - Venkat Reddy, D. 
JO  - Journal of Engineering and Applied Sciences
VL  - 11
IS  - 12
SP  - 2643
EP  - 2650
PY  - 2016
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2016.2643.2650
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2016.2643.2650
KW  - Incremental trace insertion
KW  -Field Programmable Gate-Array (FPGA) prototypes
KW  -trace-buffer
KW  -routing capacity
KW  -incremental compilation
KW  -recompilation
KW  - memory capacity
AB  - To overcome the lack of observability in FPGA-based prototypes, trace-buffer insertion plays an
important role in the design. But it also has a disadvantage of which it leads to the recompilation of the entire
system. In this study, we introduce how the incremental techniques are used to discard the necessity of
recompilation process on the circuit design and also we propose the CAD optimizations to improve the special
features, routing capacity and minimizing the delay impacts. The use of these technique implementations in this
circuitry, fastens the magnitudes than a full compilation. In this scenario, the incremental trace insertion is
notable as higher as 98 times faster than a full compilation of the design and 25% of the memory capacity is
used for tracing. The incremental circuits are more helpful for the designers only to modify by inserting the
trigger circuitry rather than compiling the entire design.
ER  -