TY  - JOUR
T1  - A Design of the DC Offset Error Compensator with Prompt Response to the Grid Voltage in PLL
AU - Park, Chang Seok AU - Jung, Tae Uk 
JO  - Journal of Engineering and Applied Sciences
VL  - 11
IS  - 7
SP  - 1687
EP  - 1692
PY  - 2016
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2016.1687.1692
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2016.1687.1692
KW  - DC offset error
KW  -compensator
KW  -PLL
KW  -single-phase grid-connected converter
KW  -coordinate transformation
AB  - This study proposes the dc offset error compensation algorithm using d-q synchronous coordinate transform Phase-Locked-Loop (PLL) in single-phase grid-connected converters. The dc offset errors are caused by the process of analog to digital conversion and the distorted grid voltage. These errors must be resolved because the dc offset error should generate the estimated grid frequency error of the PLL. In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The existing algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. The proposed algorithm has a prompt dynamic response because the DC offset is continuously estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified by PSIM simulation and the experimental test.
ER  -