TY  - JOUR
T1  - Design of 4-Bit Memory Column Dram Cell in 0.18 μm CMOS Process
AU - Mamun, Md. AU - Sedaghati, Nasima AU - Rahman, Labonnah F. AU - Husain, Hafizah 
JO  - Journal of Engineering and Applied Sciences
VL  - 8
IS  - 9
SP  - 269
EP  - 272
PY  - 2013
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2013.269.272
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2013.269.272
KW  - DRAM
KW  -4-bit memory column
KW  -3-transistor
KW  -DRAM cell
KW  -Malaysia
AB  - A Dynamic Random Access Memories (DRAM) memory cell is a capacitor 
  that is charged to produce a 1 or a 0. Over the years, several different structures 
  have been used to create the memory cells on a chip. In today’s 
  technologies, the capacitive storage element of the memory cell is used to create 
  trenched filled with dielectric material. However to progress to the next generation 
  DRAM, all the major physical limitations like circuit complexity, longer read/write 
  times and delays of the 1-Transistor (1-T) and capacitor storage cell need to 
  overcome. In this research, a 4-bit memory column cell for DRAM is presented. 
  To design the column cell, 3-transistor DRAM is chosen as it is distinguished 
  from the one transistor cell to rely on a driver transistor. Moreover, the column 
  cell operates as a constant current source during the discharge of the bit-line. 
  CEDEC 0.18 μm CMOS process has been utilized to design the column cell. 
  Therefore, the simulated results show that the designed circuit has been operates 
  successfully to comply with the DRAM.
ER  -