TY  - JOUR
T1  - Design of a 10-T Low Power Full Adder for VLSI Applications
AU - Marufuzzaman, Mohd. AU - Jaapar, Azlia Binti AU - Mamun, Md. AU - Diyana Wan Zaki, Wan Mimi 
JO  - Journal of Engineering and Applied Sciences
VL  - 8
IS  - 1
SP  - 15
EP  - 20
PY  - 2013
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2013.15.20
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2013.15.20
KW  - 10-T full adder
KW  -CMOS
KW  -VLSI application
KW  -XOR
AB  - Most of the Very Large Scale Integration (VLSI) applications 
  such as digital signal processing, image processing, video processing and microcomputers 
  extensively use arithmetic operations. The adder lies in the critical path of 
  all the arithmetic operations so that it plays a crucial role in determining 
  the overall system performance. Hence, low power dissipation, compact sized 
  Integrated Circuit (IC) is highly required in modern digital applications. Recently, 
  10-Transistor Full Adder (10-T FA) becomes a good potential candidate for designing 
  adder circuits because of reliable output and low power dissipation. This study 
  presents the design and implementation of a low power 1-bit FA circuit. The 
  design of the proposed full adder circuit is reducing power dissipation by optimizing 
  the transistor size. The simulation results showed that the design required 
  only 27x14.53 μm die area and dissipated as low as 0.1415 nW power. In 
  comparison with previous studies, this proposed full adder demonstrates an advantage 
  of low power dissipation and can be used at higher temperature with minimal 
  power loss.
ER  -