TY  - JOUR
T1  - Current Sensor and Compatible Test Processor for
IDDQ Testing of Integrated Circuits
AU - Amin, M.S. AU - Mamun, Md. AU - Marufuzzaman, Mohd. 
JO  - Journal of Engineering and Applied Sciences
VL  - 7
IS  - 2
SP  - 152
EP  - 154
PY  - 2012
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2012.152.154
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2012.152.154
KW  - Current sensor
KW  -test processor
KW  -IDDQ testing
KW  -CMOS
KW  -physical defeat
KW  -Malaysia
AB  - The present state and next state of sequential circuits are not independently controllable and
observable. As such, the testing of sequential circuit is complicated. This study presents an approach to design
and develop a VLSI system for the simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing
facility for sequential circuits. The research involves the design of an interfacing unit on PCB containing
interfacing circuits for parallel data exchange between a test processor and a microcomputer. This allows IDDQ
measurement for every vector used for logic testing, performing logic testing simultaneously, providing a
promising IDDQ fault coverage and reducing substantially the time and cost of testing. Three basic test
development strategies are considered. They are functional test development, structural test development and
physical defect test development. Mixed-mode testing facility is adopted to enhance the performance and
reduce the testing time. The simulation result shows that the presence of the sensor does not degrade the
normal operation of the CUT.
ER  -