TY  - JOUR
T1  - Analysis and Application of Hybrid MOSFET Structure for Low Gate Leakage
AU - Kapoor, Vinod AU - Chand, Narottam AU - Rana, Ashwani K. 
JO  - Journal of Engineering and Applied Sciences
VL  - 6
IS  - 1
SP  - 38
EP  - 46
PY  - 2011
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2011.38.46
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2011.38.46
KW  - subthreshold slope
KW  -analytical model
KW  -spacer dielectrics
KW  -gate tunneling current
KW  -Hybrid MOSFET (HMOS)
KW  -DIBL
AB  - A novel Hybrid MOSFET (HMOS) structure has been proposed to diminish the gate leakage current significantly. This novel Hybrid MOSFET (HMOS) consist of source/drain-to-gate non-overlap region and high-k layer/interfacial oxide as gate stack. Vertical fringing electric field through the high-k dielectric spacer induces inversion in the non-overlap region to act as extended S/D. The gate leakage behaviour of HMOS has been investigated with the help of compact analytical model and Sentaurus simulation. The model sustains a very good agreement between the model and TCAD result. It is found that HMOS structure has reduced the gate leakage current to great extent as compared to conventional overlapped MOSFET structure. Further, the proposed structure had demonstrated improved on current, off current, subthreshold slope and DIBL characteristic.
ER  -