TY  - JOUR
T1  - An Efficient Multi Port Network on Chip Router Architecture for Reliable Networks
AU - Anitha, R. AU - Renuga, P. 
JO  - Research Journal of Applied Sciences
VL  - 9
IS  - 7
SP  - 389
EP  - 396
PY  - 2014
DA  - 2001/08/19
SN  - 1815-932x
DO  - rjasci.2014.389.396
UR  - https://makhillpublications.co/view-article.php?doi=rjasci.2014.389.396
KW  - Routers
KW  -network interface
KW  -routing node
KW  -Routing algorithm
KW  -Network-on-Chip (NoC)
KW  -Adaptive Network-on-Chip (AdNoC)
KW  -on-chip interconnection networks
AB  - In this research, researchers propose a memory-efficient on-chip network architecture based router design. In addition to the resource utilization of router design, the high requirements of memories in router architecture design increases the network latency. To overcome such drawback, researchers have developed an optimized weighted scheduling methodology for router architecture and integrated it in the NI such that the network and memory latencies are significantly reduced. This proposed reliable network-on-chip router can reduce faults in both the router components and the reliability components in real time environment. The area overhead is also reduced by resource multiplexing due to the on-demand buffer assignment at each output port. The proposed work results average network latency(16%) and average memory utilization (22%).
ER  -