TY  - JOUR
T1  - Resource Efficient Implementation of Low Power LDPC Based CDMA Architecture
AU - Yasodha, T. AU - Raglend, I. Jacob AU - Jeyanthi, K. Meena Alias 
JO  - Research Journal of Applied Sciences
VL  - 8
IS  - 10
SP  - 477
EP  - 485
PY  - 2013
DA  - 2001/08/19
SN  - 1815-932x
DO  - rjasci.2013.477.485
UR  - https://makhillpublications.co/view-article.php?doi=rjasci.2013.477.485
KW  - Coding-spreading trade-off
KW  -density evolution
KW  -Low-Density Parity-Check (LDPC) codes
KW  -turbo multi-user detection
KW  -LDPC-coded turbo CDMA System
KW  -Additive White Gaussian Noise (AWGN) channel
KW  -Min-Sum algorithm
AB  - In this study, LDPC codes based low power multi-user CDMA 
  architecture is proposed. Also, a modified Min-Sum algorithm for LDPC Decoder 
  design is built and used in the proposed architecture. Min-sum iterative decoder 
  has a reduced complexity in terms of architecture-algorithm transformation, 
  compared to other LDPC Decoding algorithms. The architecture is designed for 
  LDPC encoder and the variants of Min-sum decoder. The architecture is synthesized 
  on Xilinx and Synopsys tool targeted to 90 nm device. It is found from the synthesis 
  report of the proposed architecture that it reduces the area and power overhead 
  when compared with the conventional architecture design.
ER  -