TY  - JOUR
T1  - Direct Digital Frequency Synthesizer Design and Implementation on FPGA
AU - Alsharef, A.A. AU - Ali, M.A. Mohd. AU - Sanusi, H. 
JO  - Research Journal of Applied Sciences
VL  - 7
IS  - 8
SP  - 387
EP  - 390
PY  - 2012
DA  - 2001/08/19
SN  - 1815-932x
DO  - rjasci.2012.387.390
UR  - https://makhillpublications.co/view-article.php?doi=rjasci.2012.387.390
KW  - Frequency
KW  -gate level simulation
KW  -feedback loop
KW  -verilog code
KW  -input frequency
AB  - This study presents a design and implementation of a direct 
  digital frequency synthesizer based on Quarter Sine Wave. The RTL level simulation 
  and gate level simulation of a proposed design is done by means of a Quartus-Model-Sim. 
  This design is a digital part. The digital part consists of a Phase Accumulator 
  (PA) and a Look up Table (LUT). The Phase Accumulator is implemented by means 
  of a register along with an adder and feedback loop. LUT is implemented using 
  verilog code. The size of LUT is reducing by storing quarter of sine wave in 
  the ROM. This design was tested with various tuning frequencies and the result 
  shows that the output frequency is directly proportional to the tuning input 
  frequency.
ER  -