TY  - JOUR
T1  - Pulse Width Based CMOS Subcircuits for Voltage Mode Analog
Neuron with 180 nm Technology
AU - Ayyavoo, Mithila AU - Valsalam, Vijayakumari 
JO  - Asian Journal of Information Technology
VL  - 17
IS  - 2
SP  - 114
EP  - 118
PY  - 2018
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2018.114.118
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2018.114.118
KW  - Analog neuron
KW  -CMOS circuit
KW  -multilayer perceptron
KW  -pulsed neural network
KW  -PWM technique
KW  -input
AB  - This study presents CMOS implementation of Voltage input to Pulse Converter (VPC) and activation
function circuits in 180nm technology using PWM technique. The CMOS circuits are built with ±1.8 V supply.
The circuits designed are reliably used in input or hidden layers of neural network. The pulsed output from VPC
can be given as input to synapse multiplier along with activation function that uses PWM signals to compute.
These subcircuits are of immense importance when an overall design goal is CMOS Multilayer Perceptron
(MLP) design with PWM technique. The performance parameters are simulated and observed using cadence
spectre Virtuoso 6.1.6 BSIM3v3.
ER  -