TY  - JOUR
T1  - A Low Offset Low Power Dynamic Comparator for High-Speed
Applications in 65 nm Technology
AU - Sathishkumar, Arumugam AU - Saravanan, Siddhan 
JO  - Asian Journal of Information Technology
VL  - 16
IS  - 9
SP  - 691
EP  - 698
PY  - 2017
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2017.691.698
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2017.691.698
KW  - Double-tail comparator
KW  -dynamic clocked comparator
KW  -CMOS technology
KW  -Flash ADC
KW  -HSPICE
KW  -simulation
AB  - The study presents a design of low noise, stacking reduction, low power and low voltage double tail
comparator for high speed application. The comparator design occupies less area and is suitable for the input
stage of a Flash ADC. The dynamic comparator proposed in this project not only eliminates the stacking issue
related with the convential comparator but reduces the offset noise further. The need for low noise, low-power,
area efficient and high speed flash adcs required in many application today made the work to progress in
designing a comparator for analog-to-digital converter. In this study, the analysis and design of new dynamic
comparator is proposed where the circuit of a conventional doubletail comparator is modified. The regenerative
feedback is strengthened to reduce the delay time.The rail to rail output swing is also improved by 99% of V . DD
The simulation results in a 65 nm CMOS technology confirm the analysis results. It is shown that in the
proposed dynamic comparator both the power consumption and delay time are significantly reduced. The
maximum clock frequency of the proposed comparator is increased to 2.2 and 3.5 GHz at supply voltages of 0.6
and 1 V. The simulation is carried out using predictive technology model for 65 nm in HSPICE.
ER  -