TY  - JOUR
T1  - Evaluations of Cache Coherence Protocols in Terms of Power
and Latency in Multiprocessors
AU - Aghaei, Babak AU - Zaman-Zadeh, Negin 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 24
SP  - 5181
EP  - 5186
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.5181.5186
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.5181.5186
KW  - Multiprocessor
KW  -cache coherency protocols
KW  -power
KW  -latency
KW  -experimental
AB  - The shared memory multiprocessors suffer with significant problem of accessing shared resources
in a shared memory it will result in longer latencies. Consequently, the performance of the system will get
affected. With the object of solving the problem of increased access latency due to large number of processors
with shared memory, Cache is being used. Every processor has its own private cache, now they can update or
access the data comfortably but again it leads to another serious issue i.e., cache coherency. The magnitude
of the potential performance difference between the various cache coherency approaches indicates that the
choice of coherence solution is very important in the design of an efficient shared-bus multiprocessor, since
it may limit the number of processors in the system. In this paper we evaluate a typical multiprocessor system
in terms of power and latency with different cache coherence protocols where GEM5 simulator is used. The
traffic is generated with five injection rates (0.1, 0.2, 0.3, 0.4 and 0.5). Power and latency analyzing figures are
made up and appeared in experimental result. The result shows MOESI_CMP_token has maximum latency and
power consumption.
ER  -