TY  - JOUR
T1  - Design of Reconfigurable Discrete Cosine Transform in Multicore Architecture
AU - Radhika, R. AU - Manimegalai, R. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 22
SP  - 4522
EP  - 4527
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.4522.4527
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.4522.4527
KW  - DCT
KW  -FPGA
KW  -multi core
KW  -MATLAB
KW  -single core
AB  - The image processing has an important play in multimedia systems. The image is processed and
compressed effectively to reduce the storage area. For the process of compressing it is important to convert
spatial domain to frequency domain. This study proposes the application of DCT algorithm in multi core FPGA
(Field Programmable Gate Array) to enhance the performance by simultaneously running all the cores. The
matrix format image is transformed into serial format (Hexa decimal) using MATLAB. To perform the DCT
simultaneously and in a parallel manner, the serial format values are put into the XILINX. There is severe delay
experienced by each core and the processing speed is also reduced. This happens due to more time taken for
read operation of memory. The transformation performance in multi core is compared with single core. The
parameters like delay and power consumption are reduced in multi core than in single core.
ER  -