TY  - JOUR
T1  - Design of a Multi Precision Floating Point Multiplier Using a Hybrid Technique
AU - Gokila, D. AU - Mangalam, H. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 19
SP  - 3852
EP  - 3857
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.3852.3857
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.3852.3857
KW  - FP multiplier
KW  -modified booth
KW  -truncated
KW  -partial product
KW  -bit width
AB  - Floating-Point (FP) multipliers are the key energy consumers in most of the present embedded processors based on digital signals and multimedia based appliances. A most common approach for reducing the energy utilization of FP multipliers is by cutting down the accuracy of FP multiplication operations under acceptable precision loss. This study proposes a multiple-precision FP multiplier to ably trade the energy utilization with the output quality. The proposed FP multiplier can perform low precision multiplication that generates 8, 14, 20 or 26 bit mantissa product through a hybrid technique that effectively fuses the row suppression and column suppression methodologies. Radix-8 Booth algorithm is used as the row suppression technique and truncation methodology is used for column suppression technique to tailor the output. Energy saving for this low precision multiplication is achieved by partly suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the mantissa’s bit width of the output product to change dynamically when it performs different FP multiplication operations to further decrease the energy consumption.
ER  -