TY  - JOUR
T1  - Power Optimized Vedic Parallel MAC Unit: GDI Technique
AU - Prabhu, E. AU - Mangalam, H. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 16
SP  - 2954
EP  - 2957
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.2954.2957
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.2954.2957
KW  - Gate diffusion input
KW  -parallel MAC
KW  -vedic mathematics
KW  -modified GDI
KW  -low power
AB  - In vedic mathematics of the sixteen algorithms, Urdhva Tiryakbhyam is identified as one among the efficient algorithms for multiplication in terms of delay, power and area. In this study, a parallel MAC unit has been developed which employs compressor based Urdhva Tiryakbhyam multiplier for its operation. Transistor level power optimization is realized by Gate Diffusion Input (GDI) Technique using Synopsys HSPICE. The main advantage of the proposed technique is use of less number of transistors, result in reduced power consumption. The experimental results indicate an absolute reduction in total power consumption by 39 and 34.2% for 4-bit and 8-bit MAC, respectively when compared to standard CMOS technique.
ER  -